Research Scientist (ASIC,FPGA)

 

Beijing

 

 

The mission of the Corporate Technology group is to drive Company's technology leadership.  This includes coordinating research and development among several business groups and aligning Company's strategies and technologies with industry needs.  The goal is to accelerate the convergence of computing and communications.

CTL Beijing lab (CBL) is a research and technology development lab within Company China Research Center (ICRC) in Beijing. Its mission is to make CTL Beijing lab the best Communications Technology research and technology development lab in China. Its charter includes conducting world-class research and technology development, partner with Company biz groups to max cross-architecture value and drive Company communications technology leadership in China.

 

In this position, you will be contributing to a great chip research project which foresees a bloom in the near future. Being a team member, you are expected to do but not limited to: system level analysis and architectural design, requirement definition and detailed design, RTL coding, simulation, debugging, system integration, FPGA prototyping and chip tape-out.

 

The successful candidate will have demonstrated hands-on work experience in the development of RTL for communication subsystem or components for IA platform. You should have a strong background in large scale ASIC or FPGA system design. Preferably, you possess a Master degree or above in Electrical Engineering or Computer Science (or equivalent)
The candidate needs to have excellent oral and written communication skills to effectively engage in cross-groups collaborations. 3 - 5 years experience required with a track record of successfully complete research/engineering projects based on ASIC or FPGA. Fluency in English and Mandarin required. Candidates with more or fewer qualifications will be considered for higher or lower grade positions. 

¿ Experience with track record ASIC or FPGA system design

¿ Possess knowledge of CPU bus protocols, as well as USB and PCI-e bus protocols

¿ Demonstrated ability to work at the architecture, micro-architecture, logic design, system verification levels.

¿ Experience working with Synopsys* design tool-chains is a plus

¿ Experience working with Xilinx* logic devices and tools is a plus